HD6475348R Datasheet, PDF (134/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Starting of the DTC is controlled by the six data transfer enable registers, which are located in
high addresses in page 0. Table 6-2 lists these registers.
Table 6-2 Data Transfer Enable Registers
Name
Data transfer enable register A
Data transfer enable register B
Data transfer enable register C
Data transfer enable register D
Data transfer enable register E
Data transfer enable register F
Abbreviation
DTEA
DTEB
DTEC
DTED
DTEE
DTEF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Address
H'FF08
H'FF09
H'FF0A
H'FF0B
H'FF0C
H'FF0D
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
6.2 Register Descriptions
6.2.1 Data Transfer Mode Register (DTMR)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sz SI DI — — — — — — — — — — — — —
Read/Write — — — — — — — — — — — — — — — —
The data transfer mode register is a 16-bit register, the first three bits of which designate the data
size and specify whether to increment the source and destination addresses.
Bit 15—Sz (Size): This bit designates the size of the data transferred.
Bit 15
Sz
Description
0
Byte transfer
1
Word transfer* (two bytes at a time)
* For word transfer, the source and destination addresses must be even addresses.
Bit 14—SI (Source Increment): This bit specifies whether to increment the source address.
Bit 14
SI
0
1
Description
Source address is not incremented.
1) If Sz = 0: Source address is incremented by +1 after each data transfer.
2) If Sz = 1: Source address is incremented by +2 after each data transfer.
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