HD6475348R Datasheet, PDF (260/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 2
CKS2
0
0
0
0
1
1
1
1
Bit 1
CKS1
0
0
1
1
0
0
1
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Clock Source
ø/2
ø/32
ø/64
ø/128
ø/256
ø/512
ø/2048
ø/4096
Description
Overflow Interval (ø = 10 MHz)
51.2µs (Initial value)
819.2µs
1.6ms
3.3ms
6.6ms
13.1ms
52.4ms
104.9ms
13.2.3 Reset Control/Status Register (RSTCSR)—H'FF14 (Write), H'FF15 (Read)
Bit
7
6
5
4
3
2
1
0
WRST RSTOE
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)^*1 R/W
—
—
—
—
—
—
The reset control/status register (RSTCSR) is an 8-bit readable/writable^*2 register that indicates
when a reset has been caused by a watchdog timer overflow, and controls external output of the
reset signal.
Bit 6 is not initialized by the reset caused by the watchdog timer overflow. It is initialized,
however, by a reset caused by input at the RES pin.
*1 Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1.
*2 The RSTCSR is write-protected by a password. See section 13.2.4, “Notes on Register
Access” for details.
Bit 7—Watchdog Timer Reset (WRST): This bit indicates that a reset signal has been generated
by a watchdog timer overflow in the watchdog timer mode.
The reset signal generated by the overflow resets the entire H8/534 or H8/536 chip. In addition, if
the reset output enable (RSTOE) bit is set to 1, the reset signal (Low) is output at the RES pin to
reset devices connected to the H8/534 or H8/536.
The WRST bit can be cleared by software by writing a 0. It is also cleared when a reset signal
from an external device is received at the RES pin.
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