HD6475348R Datasheet, PDF (479/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

P10 / ø*
RES
Internal reset signal
A15 to A0
R/W
External memory access
T1
T2
T3
H’0000
AS, RD and DS (read)
WR and DS (write)
D7 to D0 (write)
I/O ports
High impedance
High impedance
* The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
2. Mode 2
Figure E-1 Reset during Memory Access (Mode 1)
Figure E-4 shows how the pin states change when the RES pin goes Low during external memory
access in mode 2.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance
state. Pins P57/A15 to P50/A8 of the address bus are initialized as input ports.
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