HD6475348R Datasheet, PDF (314/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

16.1.2 Register Configuration
The on-chip RAM is controlled by the register described in table 16-1.
Table 16-1 RAM Control Register
Name
Abbreviation R/W
RAM control register RAMCR
R/W
Initial Value
H'FF
Address
H'FF11
16.2 RAM Control Register (RAMCR)
Bit
7
6
5
4
3
2
1
0
RAME —
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The RAM control register (RAMCR) is an 8-bit register that enables or disable the on-chip RAM.
Bit 7—RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized on the rising edge of the reset signal. It is not initialized in the
software standby mode.
Bit 7
RAME
0
1
Description
On-chip RAM is disabled.
On-chip RAM is enabled.
(Initial value)
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
16.3 Operation
16.3.1 Expanded Modes (Modes 1, 2, 3, and 4)
If the RAME bit is set to 1, accesses to addresses H'F680 to H'FE7F are directed to the on-chip
RAM. If the RAME bit is cleared to 0, accesses to addresses H'F680 to H'FE7F are directed to the
external data bus.
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