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HD6475348R Datasheet, PDF (274/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer | |||
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Bit 5âParity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE
0
1
Description
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is not checked.
(Initial value)
Bit 4âParity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1âs even. Odd parity means that the total number of 1âs is made odd.
This bit is ignored when PE = 0 and in the synchronous mode.
Bit 4
O/E
0
1
Description
Even parity.
Odd parity.
(Initial value)
Bit 3âStop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP
0
1
Description
1 Stop bit.
2 Stop bits.
(Initial value)
Bit 2âReserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0âClock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the H8/534 or H8/536 chip.
Bit 1
CKS1
0
0
1
1
Bit 0
CKS0
0
1
0
1
Description
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
(Initial value)
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