HD6475348R Datasheet, PDF (296/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Basic clock
Receive data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
–7.5 pulses
+7.5 pulses
Start bit
D0
D1
Sync sampling
Data sampling
Figure 14-5 Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] (1)
M: Receive margin
N: Ratio of basic clock to bit rate (16)
D: Duty factor of clock—ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F= 0
M = (0.5 –1/2 × 16) × 100 [%] = 46.875%
(2)
5. Note on Transmitting in Synchronous Mode: When setting up serial communication
interface 1 or 2 to transmit in synchronous mode, make sure the ORER bit is cleared to 0.
Transmit operation will fail to start if the ORER bit is set to 1. The same is true in
simultaneous transmitting and receiving.
282