HD6475348R Datasheet, PDF (94/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

External access cycle
Bus-right release cycle
CPU cycle
T1
T2
TW*
T3
TX*
TX
TX
T1
ø
A19 –A0
D7 –D0
RD, WR
R/W, DS
BREQ
BACK
(1)
(2)
(3)
(4)
(1) The BREQ pin is sampled at the start of the TW state and the Low level is detected.
(2) At the end of the external access cycle, the BACK pin goes Low and the CPU releases the bus.
(3) The BREQ pin is sampled at the TX state and a High level is detected.
(4) The BACK pin is returned to the High level, ending the bus-right release cycle.
* TW : Wait state.
TX : Bus-right released state.
Fig. 3-14
Figure 3-14 Bus-Right Release Cycle (During External Access Cycle)
74