HD6475348R Datasheet, PDF (337/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Oscillator
ø
NMI
NMEG
SSBY
Clock settling time
NMI interrupt handling
NMIEG = 1
SSBY = 1
SLEEP instruction
Software standby mode
(Power-down state)
NMI interrupt handling
WDT interval (tOSC2 )
Clock start-up
time
WDT overflow
Figure 18-1 NMI Timing of Software Standby Mode (Application Example)
18.3.5 Application Notes
The I/O ports remain in their current states in the software standby mode. If a port is in the High
output state, the output current is not reduced in the software standby mode.
18.4 Hardware Standby Mode
18.4.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin
goes Low.
The hardware standby mode reduces power consumption drastically by halting the CPU, stopping
all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance
state. The registers of the on-chip supporting modules are reset to their initial values. Only the
on-chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained
(see note 1).
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