HD6475348R Datasheet, PDF (121/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.2.3 Interrupt Vector Table
Table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains
how their priority is determined. For the on-chip supporting modules, the priority level set in the
interrupt priority register applies to the module as a whole: all interrupts from that module have
the same priority level. A separate priority order is established among interrupts from the same
module. If the same priority level is assigned to two or more modules and two interrupts are
requested simultaneously from these modules, they are served in the priority order indicated in the
rightmost column in table 5-2.
A reset clears the interrupt priority registers so that all interrupts except NMI start with priority
level 0, meaning that they are unconditionally masked.
102