HD6475348R Datasheet, PDF (485/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Appendix F Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in RAMCR is set to 1, drive the RES signal line
low 10 system clock cycles before the STBY signal, at a time when RAM is not being
accessed.
STBY
RES
t1 ≥ 10 tcyc t2 ≥ 0 ns
(2) When the RAME bit in RAMCR is cleared to 0, or when it is not necessary to retain RAM
contents, RES need not be driven low as in (1).
Timing of Exit from Hardware Standby Mode
Drive the RES signal line low approximately 100 ns before the rise of the STBY signal.
STBY
RES
t ≤ 100 ns
tOSC
475