HD6475348R Datasheet, PDF (82/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

3.5.9 Short-Format Instructions
The ADD, CMP, and MOV instructions have special short formats. Table 3-17 lists these short
formats together with the equivalent general formats.
The short formats are a byte shorter than the corresponding general formats, and most of them
execute one state faster.
Table 3-17 Short-Format Instructions and Equivalent General Formats
Short-Format
Execution Equivalent General-
Execution
Instruction
Length States ^*2 Format Instruction
Length States *2
ADD:Q #xx,Rd ^*1
2
2
ADD:G #xx:8,Rd
3
3
CMP:E #xx:8,Rd
2
2
CMP:G.B #xx:8,Rd
3
3
CMP:I #xx:16,Rd
3
3
CMP:G.W #xx:16,Rd
4
4
MOV:E #xx:8,Rd
2
2
MOV:G.B #xx:8,Rd
3
3
MOV:I #xx:16,Rd
3
3
MOV:G.W #xx:16,Rd
4
4
MOV:L @aa:8,Rd
2
5
MOV:G @aa:8,Rd
3
5
MOV:S Rs,@aa:8
2
5
MOV:G Rs,@aa:8
3
5
MOV:F @(d:8,R6),Rd 2
5
MOV:G @(d:8,R6),Rd 3
5
MOV:F Rs,@(d:8,R6) 2
5
MOV:G Rs,@(d:8,R6) 3
5
Notes: * 1 The ADD:Q instruction accepts other destination operands in addition to a general
register, but the immediate data value (#xx) is limited to ±1 or ±2.
* 2 Number of execution states for access to on-chip memory.
3.6 Operating Modes
The CPU operates in one of two modes: the minimum mode or the maximum mode.
These modes are selected by the mode pins (MD2 to MD0 ).
3.6.1 Minimum Mode
The minimum mode supports a maximum address space of 64 kbytes. The page registers are
ignored. Instructions that branch across page boundaries (PJMP, PJSR, PRTS, PRTD) are invalid.
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