HD6475348R Datasheet, PDF (266/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

13.3.5 Setting of Watchdog Timer Reset (WRST) Bit
The WRST bit is valid when WT/IT = 1 and TME = 1.
The WRST bit is set to 1 when the timer count overflows. An internal reset signal is
simultaneously generated for the entire H8/534 or 536 chip. The timing is shown in figure 13-7.
ø
TCNT
H'FF H'00
Overflow signal
WRST
Internal reset
signal
Figure 13-7 Setting of WRST Bit and Internal Reset Signal
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