HD6475348R Datasheet, PDF (389/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

A.3 Operation Code Map
Tables A-2 through A-6 are maps of the operation codes. Table A-2 shows the meaning of the first byte of the instruction code, indicating
both operation codes and addressing modes. Tables A-2 through A-6 indicate the meanings of operation codes in the second and third bytes.
Table A-2 Operation Codes in Byte 1
LO
HI
0
NOP
0
JMP
1
2 BRA
d:8
3 BRA
d:16
4
R0
5
6
7
8
9
A
B
C
D
E
F
1
SCB/F
See
Tbl.
A-6
See
Tbl.
A-6
*
BRN
2
LDM
STM
BHI
3
4
5
6
7
8
9
A
B
PJSR #xx:8 #aa:8.B SCB/NE SCB/EQ TRAPA TRAP/V S RTE
@aa:24 See See
See
See
Tbl. Tbl.
Tbl.
Tbl.
A-5 A-4
A-6
A-6
PJMP RTD @aa:16.B
LINK JSR RTS
SLEEP
@aa:24 #xx:8 See
#xx:8
Tbl.
A-4
BLS
Bcc BCS
BNE
BEQ BVC BVS
BPL
BMI
C
D
#xx:16 @aa:8.W
See See
Tbl. Tbl.
A-5 A-4
RTD @aa:16.W
#xx:16 See
Tbl.
A-4
BGE BLT
E
BSR
d:8
BSR
d:16
BGT
F
UNLK
LINK
#xx:16
BLE
BRN BHI
BLS
Bcc BCS
BNE
BEQ BVC BVS
BPL
BMI BGE BLT
BGT BLE
CMP:E #xx:8, Rn
R1
R2
R3
R4
R5
R6
R7
R0
MOV:E #xx:8, Rn
MOV:L.B @aa:8, Rn
MOV:S.B Rn, @aa:8
MOV:F.B @ (d:8, R6), Rn
MOV:F.B Rn, @ (d:8, R6)
Rn
(Byte) See Table A-3
@–Rn
(Byte) See Table A-4
@Rn+
(Byte) See Table A-4
@Rn
(Byte) See Table A-4
@(d:8,Rn)
(Byte) See Table A-4
@(d:16,Rn)
(Byte) See Table A-4
CMP:I #xx:16, Rn
R1
R2
R3
R4
R5
MOV:I #xx:16, Rn
MOV:L.W @aa:8, Rn
MOV:S.W Rn, @aa:8
MOV:F.W @ (:8, R6), Rn
MOV:F.W Rn, @ (d:8,R6)
Rn
(Word)
@–Rn
(Word)
@Rn+
(Word)
@Rn
(Word)
@(d:8,Rn)
(Word)
@(d:16,Rn)
(Word)
R6
R7
See Table A-3
See Table A-4
See Table A-4
See Table A-4
See Table A-4
See Table A-4
Notes:
References to tables A-3 through A-6 indicate that the instruction code has one or more additional bytes, described in those tables.
* H'11 is the first operation code byte of the following instructions:
JMP, JSR, PJSR (register indirect addressing mode)
JMP, JSR (register indirect addressing mode with displacement)
PRTS, PRTD (all addressing modes)