TCC76 Datasheet, PDF (93/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
TIMER / COUNTER
Timer/Counter n Middle Reference Register (TMREFn) 0x8000020C + (0x10 * n)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
TMREFn[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMREFn[15:0]
When TCNTn is reached at TMREFn and the PWM flag of TCFGn register is set to 1,
the timer output of TCOn is cleared to 0 at the negative edge of that pulse of selected
clock source. The TCOn is set to 1 when the TCNTn is reached at TREFn. (refer Figure
6.1). So you can generate PWM signal by modifying TMREFn between 0 ~ (TREFn-1).
In case of timer 4 and timer 5, it has 20 bit, otherwise it has 16 bit.
Timer/Counter Interrupt Request Register (TIREQ)
0x80000260
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 TWF TF5 TF4 TF3 TF2 TF1 TF0 0 TWI TI5 TI4 TI3 TI2 TI1 TI0
TWF _[14]
Watchdog Timer Flag
1
Watchdog timer has reached to its reference value.
TFn _[13:8]
Timer/Counter n Flag
1
Timer/counter n has reached to its reference value.
TWI _[6]
1
1
Type
Read
Write
Watchdog Timer Interrupt Request Flag
Watchdog timer has generated its interrupt.
Watchdog timer interrupt is cleared.
TIn _[5:0]
1
1
Type
Read
Write
Timer/Counter n Interrupt Request Flag
Timer/counter n has generated its interrupt.
Timer/counter n interrupt flag is cleared.
If a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If
its interrupt request is enabled by set bit 3 of TCFGn register, then the TIn is set. If the TC
bit of IEN register is set, the timer interrupt is really generated and this TIREQ register
can be used to determine which timer has requested the interrupt. After checking these
flags, user can clear these TFn and TIn field by writing “1” to corresponding TFn or TIn
bit field.
Preliminary
6-5