TCC76 Datasheet, PDF (153/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MISCELLANEOUS PERIPHERALS
12 MISCELLANEOUS PERIPHERALS
12.1 ADC
12.1.1 Overview
The TCC76x has multiple-input general purpose low-power ADC for battery level detection, remote control interface,
touch screen interface, etc. It is a CMOS type 10bit A/D converter with 8-channel analog input multiplexer. The
TCC761 can support up to 8 inputs for ADC, and the other derivatives can support up to 3 inputs.
• Resolution : 10-bit
• Maximum Conversion Rate : 500KSPS
• Main Clock : 2.5MHz (Max.)
• Standby Mode
• Input Range : 0.0V ~ VDDA_ADC
ADCDATA/
ADCSTATUS
ADCCFG
ADCCON/
ADCCONA
IRQ to Interrupt
Controller
Read Data
Buffer (x4)
Timing
Control
DO[9:0]
EOC
STC
STBY
CLK
ADC
Core
AIN[7:0]
Command SEL[2:0]
Buffer (x4)
Figure 12.1 ADC Controller Block Diagram
Except for the APB interface, the ADC controller module runs with ADCLK from the Clock Generator module. The
clock input is always divided before sent to the ADC core. The EACLKmode register of Clock Generator and
CLKDIV bits of ADCCFG register must be programmed to get desired frequency. The maximum frequency of CLK
signal in Figure 12.1 must not exceed 2.5MHz.
When one of the ADCCON or ADCCONA register is written with a channel number (SEL[2:0]), the SEL value is
posted to the Command Buffer. The ADC Core starts conversion cycle as long as the Comand Buffer is not empty.
After the conversion cycle is completed, the result is written in Read Data Buffer. The data can be read from either
ADCDATA or ADCSTATUS register. Up to four different SEL values can be posted to the Command Buffer.
When the buffer is full, data written to ADCCON/ADCCONA registers are ignored. Various operating options can
be set by using ADCCFG register.
Preliminary
12-1