TCC76 Datasheet, PDF (120/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
Power Down Mode Control Register (PWDCTL)
0x80000440
Bit Name
Type Default Description
31:18 Reserved
R
0
17 XTFCLK
R/W
0
Select XTIN for FCLK.
If DIV1 bit of PLLmode register is “0” and this bit is set as “1”,
clock source for FCLK and HCLK is changed to XTIN.
16 XTHCLK
R/W
0
Select XTIN for HCLK.
If DIV1 bit of PLLmode register is “0” and this bit is set as “1”,
clock source for HCLK is changed to XTIN. The functionality of
this bit is disabled when HS bit of SCLKmode register is “1”.
15:10 Reserved R/W
0
9:8 DVPLL
R/W
0
Clock Divisor Value for the PLL Divider described in Figure 8.1.
Use the divider when the PLL output frequency is too high.
DVPLL PLLDIVCLK
00
Disabled
01
PLLOUT / 2
10
PLLOUT / 3
11
PLLOUT / 4
7 XTTC32
R/W
0
Clock select for 32-bit counter. Do not change when the counter
is enabled.
0:
XTIN
1:
XIN
When this bit 0, XTIN oscillator is always enabled regardless of
the other register bits which controls XTIN oscillator.
6 CPUREQ R/W
0
CPU bus request control in IDLE mode.
0:
Disable the bus request signal from the CPU
1:
Enable the bus request signal from the CPU
5 PAUSE
R/W
0
PAUSE the arbiter in IDLE mode.
0:
Enable the AHB arbiter
1:
Pause the AHB arbiter
4 CTLHCKE R/W
0
HCLK Enable in Power Down Mode. For test purpose only.
3 XTINEN
R/W
0
Force XTIN Oscillator Enabled.
For test purpose only.
2 XTINCKE R/W
0
Force XTIN Clock Enabled.
For test purpose only.
1 XINEN
R/W
0
Force XIN Oscillator Enabled.
For test purpose only.
0 XINCKE
R/W
0
Force XIN Clock Enabled.
For test purpose only.
Note: Except for XTTC32 bit, all the default values were selected to keep the TCC72x compatibility.
Preliminary
8-14