TCC76 Datasheet, PDF (130/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
USB CONTROLLER
EP0 CSR Register (EP0CSR)
15 14 13 12 11 10 9
Reserved
0x80000544
876543210
CLSE CLOR ISST CEND DEND STST IRDY ORDY
This register has the control and status bits for EP0 endpoint. Since a control transaction
involves both IN and OUT tokens, there is only one CSR register, mapped to INCSR1
register. EP0CSR register can access by writing “0” to UBIDX register.
CLSE [7] Type
Clear Setup End Bit
1
W The CEND flag is cleared when writing a 1 to this bit.
CLOR [6] Type
Clear Output Packet Ready Bit
1
W The ORDY flag is cleared when writing a 1 to this bit.
ISST [5]
1
0
Type
R/W
Issue STALL Handshake
If USB decodes an invalid token, the CPU writes a 1 to this
and CLOR bit concurrently. The USB issues a STALL
handshake to the current control transfer.
End the STALL condition by writing a 0 to this bit.
CEND [4] Type
Control Transfer End
Indicates that the control transfer ends before DEND bit is
set.
1
R It is cleared by writing a 1 to CLSE bit.
When this is set, an interrupt occurs and the USB flushes
FIFO and invalidates all access to FIFO.
*) When CEND bit is set, the ORDY bit also may be set. This happens when the current transfer has
ended, and a new control transfer is received before the MCU can service the interrupt. In such a
case, the CPU should first clear the CEND flag, and then start servicing the new control transfer.
DEND [3]
1
Type
R/W
Data End
CPU write a 1 to this bit:
- after loading the last packet of data into the FIFO, at the
same time IRDY flag is set.
- while it clears ORDY after unloading the last packet of
data.
- for a zero length data phase, when it clears ORDY flag
and sets IRDY flag.
In the case of a control transfer where there is no data
phase, the CPU (after unloading the setup token) sets
DEND at the same time it clears ORDY for the setup
token.
STST [2]
1
0
Type
R
W
STALL Handshake Issued
Indicates that a control transaction is ended due to a
protocol violation. An interrupt is generated when this bit
is set.
Clear STST flag by writing 0.
IRDY [1]
1
Type
W
IN Packet Ready
After writing a packet of data into EP0 FIFO, set this bit
to 1.
Preliminary
9-8