TCC76 Datasheet, PDF (23/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name
GPIO_B[20:17]
GPIO_B[16:14]
GPIO_B[13:10]
GPIO_B[9]
GPIO_B[8]
GPIO_B[7]
GPIO_B[6]
GPIO_B[5:2]
GPIO_B[1]
GPIO_B[0]
GPIO_C[15:0]
GPIO_D[14]
GPIO_D[13:10]
GPIO_D[9:8]
GPIO_D[7:6]
GPIO_D[5:4]
GPIO_D[3:1]
GPIO_D[0]
GPIO_D[21:18]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
Shared Signal
ACBIAS
PXCLK
VSYNC
HSYNC
CDAI
CLRCK
CBCLK
SDI13
FRM3
SCK3
SDO3
UT_RX
UT_TX / SD_nCS
ND_nWE
IDE_nCS1
nCS[3:0]
SD_nCS / SD_nCLK
SD_CKE
XD[31:24]
XD[23:16]
FGPIO[14:11] / CISD[7:4]
FGPIO[10] / SCL / CISHS
FGPIO[9] / SDA / CISVS
FGPIO[8] / CISCLK
ADIN[7:0]
XIN
XOUT
XFILT
XTIN
XTOUT
MODE1
PKG1
PKG0
nRESET
TDI
TMS
Pin # Type Description – TCC761
168
167
I/O GPIO_B[20:17] / LCD Interface Signals
166
165
87
86
I/O GPIO_B[16:14] / CD Interface Signals
85
11:8
I/O GPIO_B[13:10] / General Purpose Serial I/O 3
100
99
96
94
84:81
80
I/O GPIO_B[9] / UART RX Signal
I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select.
I/O GPIO_B[7] / Write enable for NAND flash
I/O GPIO_B[6] / Chip select 1 for IDE Interface
I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
I/O
SDRAM.
95
I/O GPIO_B[0] / SDRAM clock control
76:69
31:24
I/O GPIO_C[15:0] / External Data Bus [31:16]
200
196:193
188:187
173, 93 I/O GPIO_D[14:0]
64, 62
44:42
21
GPIO_D[21:18] / Fast GPIO bits 14 ~11 / Camera Interface Data
156:153 I/O
Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset.
152
I/O GPIO_D[17] / Fast GPIO bit 10/ I2C SCL / Camera Interface Hsync.
151
I/O GPIO_D[16] / Fast GPIO bit 9 / I2C SDA / Camera Interface Vsync.
150
I/O GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
143:136 AI General purpose multi-channel ADC inputs 7 ~ 0
Clock Pins
Main Crystal Oscillator Input for PLL. 12MHz Crystal
119
I must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
120
O Main Crystal Oscillator Output for PLL
132
AO PLL filter output
Sub Crystal Oscillator Input. 32.768kHz is recommended.
110
I
Input voltage must not exceed VDD_OSC (1.95V max).
111
O Sub Crystal Oscillator Output
Mode Control Pins
159
I Mode Setting Input 1. Pull-down for normal operation
149
I Package ID1. Pull-up for normal operation
148
I Package ID0. Pull-down for normal operation
117
I System Reset. Active low.
JTAG Interface Pins
160
I JTAG serial data input for ARM940T
161
I JTAG test mode select for ARM940T
Preliminary
1-13