TCC76 Datasheet, PDF (85/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTERRUPT CONTROLLER
Interrupt Enable Register (IEN)
0x80000100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEN TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R E3 E2 E1 E0
MEN [15]
Master Enable
0
All interrupts are disabled.
1
Any interrupt enabled by corresponding bit[18:0] can be generated to CPU
*) Master Enable functionality is not effective if RDYIRQEN bit of Miscellaneous
Configuration Register is set as “1”.
Bit Field
CIF _[18]
I2C _[17]
ADC _[16]
RDY _[15]
TC32 _[14]
DMA _[13]
LCD _[12]
CDIF _[11]
UBH _[10]
GS _[9]
UB _[8]
UT _[7]
TC _[6]
I2T _[5]
I2R _[4]
E3 _[3]
E2 _[2]
E1 _[1]
E0 _[0]
Interrupt Request Control
1 = Interrupt enabled, 0 = Interrupt disabled
Camera Interface interrupt control
I2C interrupt control
ADC interrupt control
External Bus READY interrupt control. This bit is effective only when
RDYIRQEN bit of Miscellaneous Configuration Register is set to high.
32-bit Timer interrupt control
DMA interrupt control
LCD interrupt control
CDIF interrupt control
USB Host interrupt control
GSIO interrupt control
USB interrupt control
UART/IrDA interrupt control
Timer/Counter interrupt control
I2S TX interrupt control
I2S RX interrupt control
External interrupt request 3 control
External interrupt request 2 control
External interrupt request 1 control
External interrupt request 0 control
Clear Interrupt Request Register (CREQ)
0x80000104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R E3 E2 E1 E0
By writing “1” to each field, the interrupt request flag of corresponding interrupt is cleared. Writing to “0”
doesn’t mean anything and the corresponding flag remains its previous state.
Interrupt Request Register (IREQ)
0x80000108
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R E3 E2 E1 E0
If each field is “1”, it means that the corresponding interrupt has been requested. If each peripheral has its own
request flags, it means at least one of those flags has been set.
Preliminary
5-3