TCC76 Datasheet, PDF (171/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
STN ^{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
PXDW=0(4bits)
X
PD[3:0]
STN ^{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
PXDW=3(8bits)
X
PD[7:0]
TFT ^{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
PXDW=2(6bits)
X
R[5:0], G[5:0], B[5:0]^*
TFT ^{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
PXDW=3(8bits)
X
R[7:0], G[7:0], B[7:0]^*
*_)R->G->B
TFT ^{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
PXDW=4(565)
R[4:0]
G[5:0]
B[4:0]
TV ^{15 14 13 12 11 10 9}
PXDW=3(8bits)
X
TV ^{15 14 13 12 11 10 9}
PXDW=6(16bits)
Y[7:0]
876543210
U0[7:0], Y0[7:0], V0[7:0], Y1[7:0]^**
**_{)U0->Y0->V0->Y1}
876543210
U[7:0], V[7:0]^***
***_)U->V
Figure 14.3 Output Pixel Data Organization(GPIO_A[31:16] = PXDATA[15:0])
14.3
Interrupt configuration
LCDC has three maskable interrupt sources; Disable Done(DD), Register Update(RU),
and FIFO underrun interrupt(FU). Each interrupt source can be masked as corresponding
bit of LIM is set to 1. DD interrupt is generated when LEN bit is cleared and current
frame is completed. RU interrupt is generated after all of control registers are updated. So,
control registers which was programmed are applied to displaying a frame after
displaying the current frame is completed. FU interrupt is generated when FIFO underrun
is occurred. HCLK frequency is always faster than LCLK frequency to prevent FIFO
underrun from taking place.
For using LCDC interrupt, all of LCDC interrupt source must be cleared before enabling
interrupt. The corresponding bits of LSTATUS are written to 1 to clear it. And CREQ
register of interrupt controller must be also cleared.
1. clear LSTATUS register of LCDC
2. clear CREQ of interrupt controller
3. set LIM register of LCDC to unmask the corresponding LCDC interrupt.
4. set IEN register of interrupt controller to enable the LCDC interrupt
Whenever LCDC interrupt is generated, the corresponding bits of LSTATUS register must be
cleared. Otherwise, LCDC interrupt is not generated any more.
Preliminary
14-3