TCC76 Datasheet, PDF (118/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
TCLK (Timer) Control Register (TCLKmode)
0x80000424
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DIVT
0
TC_PHASE[5:0]
Bit Name
Type Default Description
31:10 Reserved
R
0 Reserved
9:8 DIVT
R/W
0 TCLK Divisor Clock Select
DIVT f_DIVT (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
7:6 Reserved
R
0 Reserved
5:0 T_PHASE R/W
0 TCLK Clock Frequency Select
DIVMODE[10] T_PHASE f_TCLK (TCLK Frequency)
0
0
f_DIVT
0
1 ~ 0x20 f_DIVT * T_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIVT / (T_PHASE + 1)
TCLK is also controlled by TCK bit of CKCTRL register that can enable or disable TCLK. If this bit is set to high,
TCLK is disabled and if it is low, TCLK is enabled.
GCLK (GSIO) Control Register (GCLKmode)
0x80000428
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DIVG
0
GC_PHASE[5:0]
Bit Name
Type Default Description
31:10 Reserved
R
0 Reserved
9:8 DIVG
R/W
0 GCLK Divisor Clock Select
DIVG f_DIVG (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
7:6 Reserved
R
0 Reserved
5:0 G_PHASE R/W
0 GCLK Clock Frequency Select
DIVMODE[11] G_PHASE f_GCLK (GCLK Frequency)
0
0
f_DIVG
0
1 ~ 0x20 f_DIVG * G_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIVG / (G_PHASE + 1)
GCLK is also controlled by GCK bit of CKCTRL register that can enable or disable GCLK. If this bit is set to high,
GCLK is disabled and if it is low, GCLK is enabled.
Preliminary
8-12