TCC76 Datasheet, PDF (208/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ECC (ERROR CORRECTION CODE)
16.2 Register Description
Name
ECC_CTRL
ECC_BASE
ECC_MASK
ECC_CLR
SLC_ECC0
SLC_ECC1
SLC_ECC2
SLC_ECC3
SLC_ECC4
SLC_ECC5
SLC_ECC6
SLC_ECC7
MLC_ECC0W
MLC_ECC1W
MLC_ECC0R
MLC_ECC1R
Table 16.1 ECC Register Map (Base Address = 0x80000900)
Address Type Reset
Description
0x00
R/W 0x00000000 ECC Control Register
0x04
R/W 0x00000000 Base Address for ECC Calculation
0x08
R/W 0x00000000 Address mask for ECC area.
0x0C
0x10
0x14
0x18
0x1C
W
-
Clear ECC output register
R
0x00000000 1^st Block ECC output for SLC NAND
R
0x00000000 2^nd Block ECC output for SLC NAND
R
0x00000000 3^rd Block ECC output for SLC NAND
R
0x00000000 4^th Block ECC output for SLC NAND
0x20
0x24
0x28
0x2C
R
0x00000000 5^th Block ECC output for SLC NAND
R
0x00000000 6^th Block ECC output for SLC NAND
R
0x00000000 7^th Block ECC output for SLC NAND
R
0x00000000 8^th Block ECC output for SLC NAND
0x40
W
-
MLC NAND ECC calculation register 0
0x44
W
-
MLC NAND ECC calculation register 1
0x48
R/W 0x00000000 Calculated ECC output 0 for MLC NAND
0x4C
R/W 0x00000000 Calculated ECC output 1 for MLC NAND
ECC Control Register (ECC_CTRL)
0x80000900
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
ECC_CNT[8:4]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_CNT[3:0]
MLC_STAT[3:0]
HLD 0 EC0 ME SLC_CNT[2:0] SE
ECC_CNT [20:12]
ECC Word Counter
N
Means that N number of words are calculated
MLC_STAT [11:8]
1000
0100
0010
0001
Represent Internal State for MLC
ST_ECC : Compare state. It compares two ECC for error-checking.
ST_WR : Write state. It calculates ECC for write cycle.
ST_RD : Read state. It calculates ECC for read cycle.
ST_IDLE : Idle state. It waits until there is access for MLC device.
HLD [7]
1
ECC Hold
Hold Enabled. ECC output register is not changed.
EC0 [5]
1
ECC Zero
Means that ECC output register (MLC_ECC0R & MLC_ECC1R
for MLC, SLC_ECC0 & SLC_ECC1 for SLC) contains 0.
ME [4]
1
0
MLC ECC Enable
Enable ECC for MLC
Disable ECC of MLC
Preliminary
16-2