TCC76 Datasheet, PDF (230/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
BOOTING PROCEDURE
20.4 I²C or NAND Boot (BM == 001)
There are 2 modes in the TCC76x when BM[2:0] is equal to 001. One is booting from
serial EEPROM through I2C interface and the other is booting from NAND flash.
The EEPROM must have I2C address of 0xA0 (for write) and 0xA1 (for read), and the
NAND chip enable is controlled either by GPIO_A7 or GPIO_A6 or GPIO_D13 or
GPIO_D12, and NAND out-enable is connected via nCS2 pin.
The procedure checks if there exist EEPROM first, the I2C interface must be connected
via GPIO_D17 for clock and GPIO_D16 for data. If there exist an EEPROM, the
procedure follows I2C boot sequence or it checks if NAND flash is connected with some
GPIO pins. The sequence of checking starts from GPIO_A7, then GPIO_A6, then
GPIO_D13, and end with GPIO_D12.
The boot sequence of I2C interface is as follows.
i) Read init line from EEPROM. The init line consists of the following information.
1^st word ~ 2^nd word: security information
3^rd word : size of code.
ii) Check if the security information is correct.
iii) Decrypt codes and copy them to internal SRAM (starts from 0x30000000).
iv) After all amount of codes are decrypted and copied, the program executes from the
start of internal SRAM (0x30000000).
It is considered that the output enable of NAND flash is to be connected with nCS2. The
boot sequence of NAND flash is as follows.
i) Check if device id exist in the device id table while changing chip select pin from
GPIO_A7 to GPIO_D12. (GPIO_A7 GPIO_A6 GPIO_D13 GPIO_D12)
ii) Set CSCFG2 register according to device id value.
iii) Read data by 512 bytes unit from the last page down to half of NAND size until the
ECC (SSFDC standard) of them and the 1^st and 2^nd word in them are all correct.
Select lower or upper half of 512 bytes as an initialization code block according to
the result of ECC checking.
1^st word ~ 2^nd word: security information.
iv) If the correct block is found, copy the remaining of code in selected block from the
3^rd word to internal SRAM (starts from 0x30000000). After all amount of codes are
copied (initialization codes are not encrypted), the program sequence is changed to
internal SRAM (0x30000000). And these codes take responsibility of the remaining
boot process.
The overall flow of I2C and NAND boot is illustrated in the Figure 20.3
The supported NAND flash types are as follows.
Preliminary
20-4