TCC76 Datasheet, PDF (113/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
System Clock Control Register (SCLKmode)
0x80000408
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HS HD
H_PHASE
0
F_PHASE
It generates FCLK, HCLK for system operation. FCLK is dedicated for the ARM940T processor, HCLK is used as
internal AHB bus clock that is fed to almost internal peripherals including ARM940T processor, memory controller,
DMA controller, etc. Each clock can be generated either by DCO mode or Divider mode. The 6bit DCO (Digital
Controlled Oscillator) can generate a variable frequency as long as its frequency is below about one tenth of divisor
clock’s frequency. For reliable operation, keep the n power of 2 relationships with divisor clock, so the DCO act like
a simple clock divider. (To keep the n power of 2 relationship between f_SCLK and f_DIV in DCO mode, the phase
value must be one of the 0, 32, 16, 8, 4, 2, 1). The target frequency can be acquired by writing the phase value
calculated by the following equation to the PHASE register.
For the DCO Mode (when DIVMODE[1] is “0”),
PHASE = 64 * f_SCLK / f_DIV
(PHASE must be less or equal to 32)
For the Divider Mode (when DIVMODE[1] is “1”),
PHASE = f_DIV / f_SCLK - 1
Although the DCO mode can generate flexible frequency outputs, it has irreqular clock duty and jitter which may cause
unexpected timing problem especially with external bus components. Timing parameters programmd in memory
control registers should have sufficient margin to compensate the irregularity of the DCO. It is strongly recommended
to use Divider mode (refer to DIVMODE register) rather than DCO mode.
Bit Name
31:16 Reserved
15 HS
14 HD
13:8 H_PHASE
7:6 Reserved
5:0 F_PHASE
Type
R
R/W
R/W
R/W
R
R/W
Default
0x0008
0
0
0x20
0
0
Description
Reserved
HCLK Clock Select
0 Enable XTHCLK bit of PWDCTL register.
1 Disable XTHCLK bit of PWDCTL register. PWDCTL[16] signal,
which is shown in Figure 8.1, is replaced with PWDCTL[17].
HCLK Clock Disable in IDLE Mode
0 In idle mode, HCLK is enabled
1 In idle mode, HCLK is disabled
By using this flag, the power of peripherals driven by HCLK especially
for memory controller can save more power in idle mode. This flag
must be used carefully because by setting this flag, most of the internal
modules including the memory controller are stopped in idle mode.
Also note that interrupt request from the internal core modules are not
available if HCLK is disabled. The external interrupt pins and the 32-bit
counter running with XTIN clock are valid wake up events in this case.
If you want to use another interrupt source as an wakeup event, do not
disable HCLK with HD bit. Instead, use HCLKSTOP register to
disable each peripheral individually.
HCLK Frequency Select
DIVMODE[1] H_PHASE f_HCLK (HCLK Frequency)
0
0
f_DIV or f_FCLK (depends on HS bit)
0
1 ~ 0x20 f_DIV * H_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIV / (H_PHASE + 1)
Reserved
FCLK Frequency Select
DIVMODE[0]
F_PHASE f_FCLK (FCLK Frequency)
0
0
f_DIV
0
1 ~ 0x20 f_DIV * F_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIV / (F_PHASE + 1)
Preliminary
8-7