TCC76 Datasheet, PDF (164/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
DMA CONTROLLER
HOP Count Register (HCOUNT)
0x80000E20
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_HCOUNT[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_HCOUNT[15:0]
C_HCNT [31:16] Type
Current Hop Count
cn
R Represent cn number of Hop transfer remains
ST_HCNT [15:0] Type
Start Hop Count
sn
R/W DMA transfers data by amount of sn Hop transfers
At the beginning of transfer, the C_HCNT is updated by ST_HCNT register. At the end of every
hop transfer, this is decremented by 1 until it reaches to zero. When this reaches to zero, the DMA
finishes its transfer and may or may not generate its interrupt according to IEN flag of CHCTRL
register.
Channel Control Register (CHCTRL)
31 30 29 28 27 26 25 24
0
15 14 13 12 11 10 9 8
CONT 0 SYNc HRD LOCK BST
TYPE
23 22 21 20
DMASEL[12:0]
7654
BSIZE
WSIZE
19
3
FLAG
0x80000E24
18 17 16
210
IEN REP EN
DMASEL [28:16]
non-zero
Select Source of DMA Request
Each bit field selects corresponding signal as a source for DMA
request. The bit-map of this register is identical with the IEN of
interrupt controller. So if you want to use EXINT0 pin as a source of
DMA request, set DMASEL[0] as 1 and select transfer type of
HW_ARBIT or HW_BURST.
If multiple bits of this field are set, all the corresponding signal can
generate DMA request for this channel.
CONT [15]
0
1
Issue Continuous Transfer
DMA transfer begins from ST_SADR / ST_DADR address
DMA transfer begins from C_SADR / C_DADR address
It must be used after the former transfer has been executed, so that
C_SADR and C_DADR contain a meaningful value.
SYNC [13]
0
1
Hardware Request Synchronization
Do not Synchronize Hardware Request.
Synchronize Hardware Request.
HRD [12]
0
1
Hardware Request Direction
ACK/EOT signals are issued when DMA-Read Operation.
ACK/EOT signals are issued When DMA-Write Operation.
LOCK [11]
Issue Locked Transfer
1
DMA transfer executed with lock transfer
Lock field controls the LOCK signal (refer to AHB specification). When the LOCK is set to 1,
the DMA transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This
field is only meaningful in case of non-burst type transfers.
Preliminary
13-4