TCC76 Datasheet, PDF (185/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
FIELD
ACDIV [15:8]
CLKDIV [7:0]
Description
AC Bias clock divisor(STN only).
The number of clock cycles to count between each toggle of
AC_BIAS pin.. ACBIAS is toggled every n HSYNC cycles if ACDIV
is {(lpw+1) *n – 1}.
Pixel clock divisor
Note that programming CLKDIV less than 3 is illegal for STN LCD.
PXCLK = LCLK / (2*CLKDIV)
(if CLKDIV = 0, PXCLK = LCLK)
LCD Horizontal Timing Register1 (LHTIME1)
31 30 29 28 27 26 25 24 23
0
15 14 13 12 11 10 9 8 7
0
22 21 20 19
LPW
6543
LPC
0x80000F08
18 17 16
210
FIELD
LPW [23:16]
LPC [10:0]
Description
Line Pulse Width is the number of pixel clock cycles.
Line Pulse Count is the number of pixel clock cycles in each line minus
1 on the screen
TFT /NTSC(16bit)/PAL(16bit) : active horizontal pixels - 1
Color STN : (3 * Horizontal display size / pixel width) -1
Mono STN: (Horizontal display size / pixel width )- 1
LCD Horizontal Timing Register2 (LHTIME2)
0x80000F0C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
LSWC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
LEWC
FIELD
LSWC [24:16]
LEWC [8:0]
Description
Line Start Wait Cycle is the number of dummy pixel-clock cycles
minus 1 to insert from the start of each horizontal line of pixels.
Line End Wait Cycle is the number of dummy pixel-clock cycles minus
1 to insert before the end of each horizontal line of pixels.
Preliminary
14-17