TCC76 Datasheet, PDF (149/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
GSIO PORT
GSIOn Control Register (GSCR0 ~ GSCR3)
0x80000708 + (0x10 * n)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN MS
WORD
WS
DIV
CP CM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DELAY FP
FRM1
FRM2
EN [31]
0
1
GSIO Enable
Disable the corresponding GSIO block
Enable the corresponding GSIO block
MS [30]
0
1
First Bit Select
Data is transmitted or received by LSB first order
Data is transmitted or received by MSB first order
WORD [29:26]
GSIO word size
n
GSIO data transaction has (n+1) bit unit, n = 0 ~ 15
*) This is valid only when the WS bit of GSCRn register is 0.
WS [25]
0
1
Word Size Select
GSIO word size is determined by WORD of GSCRn register
GSIO word size is determined by BW of GSDO register
DIV [24:18]
0
1 ≤ n ≤ 127
GSIO base clock speed control
Reserved.
GSIO base clock has 1/(2n+2) of GCLK frequency.
CP [17]
0
1
GSIO clock polarity
SDO changes or SDI is sampled at SCK falling
SDO changes or SDI is sampled at SCK rising
CM [16]
0
1
Last clock mask
No mask. GSIO clock is generated for every SDO.
GSIO clock is masked at the last SDO period.
DELAY [14:13]
Initial delay for serial transmission
0
Reserved. DELAY should not be set to 0.
1≤n≤3
GSIO transmission starts after n base clock has generated.
FP [12]
0
1
Frame pulse polarity
FRM has low active pulse
FRM has high active pulse
FRM1 [11:6]
Frame pulse start position
n
Frame pulse starts after n base clock has generated
FRM2 [5:0]
Frame pulse end position
n
Frame pulse ends after n base clock has generated
Preliminary
11-3