TCC76 Datasheet, PDF (173/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1BPP p24 p25 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23
2BPP p12 p13 p14 p15
p8
p9
p10 p11
4BPP
p6
p7
p4
p5
8BPP
p3
p2
16BPP
p1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1BPP p8 p9 p10 p11 p12 p13 p14 p15 p0 p1 p2 p3 p4 p5 p6 p7
2BPP p4
p5
p6
p7
p0
p1
p2
p3
4BPP
p2
p3
p0
p1
8BPP
p1
p0
16BPP
p0
b) BR=1
Figure 14.4 STN LCD pixel data organization
STN ^{7 6 5 4 3 2 1 0}
8BPP R[1:0] G[2:0]
B[2:0]
STN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16BPP
X
R[3:0]
G[3:0]
B[3:0]
Figure 14.5 Color STN Pixel Data
ACBIAS signal is used by the LCD driver to alternate the polarity of the row and column
voltage used to turn the pixel on and off. It is controlled by the ACDIV field of
LCLKDIV register. This value must be (lpw+1) times.
ACDIV = {(lpw+1) * n} –1
n = number of HSYNC(CL1)
PXCLK frequency is determined by the CLKDIV field of LCLKDIV register as follows.
The minimum value of CLKDIV is 3 in STN mode.
f_PXCLK = f_LCLK / (2 * CLKDIV)
(1)
VSYNC frequency is related to the field of FEWC, LSWC, LEWC, LPC, and FLC as
well as LCLK and PXCLK.
f_VSYNC
= f_PXCLK / [{(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}
* {(FLC + 1) + (FPW+1)}]
Therefore, if FR is the required refresh rate, f_{PXCLK_REQ}, which is the required PXCLK, is
the flowing.
f_{PXCLK_REQ} = FR x [ {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}
* {(FLC + 1) + (FEWC+1)} ]
(2)
The LCDC contains dithering pattern registers for STN LCD: a 48-bit modulo 7 dithering
pattern register (LDP7L and LDP7H), a 32-bit modulo 5 dithering pattern register (LDP5),
a 16-bit modulo 4 dithering pattern register (LDP4), and a 16-bit modulo 3(LDP3)
dithering pattern register. These dithering pattern registers can contain the programmable
Preliminary
14-5