TCC76 Datasheet, PDF (5/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
TABLE OF CONTENTS
8.2 Register Description................................................................................................................ 8-4
9 USB CONTROLLER ......................................................................................................................... 9-1
9.1 Overview ................................................................................................................................. 9-1
9.2 Register Description for USB Device Controller ..................................................................... 9-2
9.3 USB Device DMA Operation ................................................................................................. 9-13
9.3.1 OUT Endpoint DMA Operation ................................................................................... 9-13
9.3.2 IN Endpoint DMA Operation ....................................................................................... 9-13
9.4 Register Description for USB Host Controller ....................................................................... 9-14
10 UART/IrDA..................................................................................................................................... 10-1
10.1 Overview ............................................................................................................................. 10-1
10.2 Register Description............................................................................................................ 10-2
11 GSIO PORT................................................................................................................................... 11-1
11.1 Overview ............................................................................................................................. 11-1
11.2 Register Description............................................................................................................ 11-2
12 MISCELLANEOUS PERIPHERALS ............................................................................................. 12-1
12.1 ADC ..................................................................................................................................... 12-1
12.1.1 Overview ................................................................................................................... 12-1
12.1.2 ADC Controller Register Description ........................................................................ 12-2
12.2 Miscellaneous Register Description.................................................................................... 12-4
13 DMA CONTROLLER ..................................................................................................................... 13-1
13.1 Overview ............................................................................................................................. 13-1
13.2 Register Description............................................................................................................ 13-2
14 LCD CONTROLLER...................................................................................................................... 14-1
14.1 Overview ............................................................................................................................. 14-1
14.2 Related Blocks .................................................................................................................... 14-2
14.3 Interrupt configuration ......................................................................................................... 14-3
14.4 STN LCD ............................................................................................................................. 14-4
14.5 TFT LCD.............................................................................................................................. 14-9
14.6 NTSC/PAL interface .......................................................................................................... 14-11
14.7 Register Description.......................................................................................................... 14-14
15 MEMORY CONTROLLER............................................................................................................. 15-1
15.1 Overview ............................................................................................................................. 15-1
15.2 SDRAM Controller............................................................................................................... 15-3
15.3 Miscellaneous Configuration............................................................................................... 15-6
15.4 External Memory Controller ................................................................................................ 15-9
15.5 Internal Memory ................................................................................................................ 15-14
16 ECC (Error Correction Code) ........................................................................................................ 16-1
16.1 Functional Description......................................................................................................... 16-1
16.2 Register Description............................................................................................................ 16-2
17 I2C CONTROLLER ....................................................................................................................... 17-1
17.1 Functional Description......................................................................................................... 17-1
17.2 Related Blocks .................................................................................................................... 17-1
17.3 Register Description............................................................................................................ 17-2
18 CAMERA INTERFACE .................................................................................................................. 18-1
18.1 Overview ............................................................................................................................. 18-1
18.2 Related Blocks .................................................................................................................... 18-2
18.3 Register Description............................................................................................................ 18-5
19 FAST GPIO.................................................................................................................................... 19-1
19.1 Description .......................................................................................................................... 19-1
20 BOOTING PROCEDURE.............................................................................................................. 20-1
20.1 Overview ............................................................................................................................. 20-1
20.2 External ROM Boot without Encryption (BM == 000) ......................................................... 20-2
20.3 USB Boot (BM == x1x)........................................................................................................ 20-3
20.4 I²C or NAND Boot (BM == 001) .......................................................................................... 20-4
20.5 External ROM Boot with Encryption (BM == 100) .............................................................. 20-6
20.6 Development mode (BM == 101)........................................................................................ 20-7
21 JTAG DEBUG INTERFACE .......................................................................................................... 21-1
21.1 Debugging with OPENice32 & AIJI Spider.......................................................................... 21-2
Preliminary
v