TCC76 Datasheet, PDF (45/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name
GPIO_B[26]
GPIO_B[25]
Shared Signal
USB_DP
DAI
GPIO_B[24] / BM[2] DAO
GPIO_B[23]
MCLK
GPIO_B[22] / BM[1] LRCK
GPIO_B[21] / BM[0] BCLK
GPIO_B[9]
GPIO_B[8]
GPIO_B[7]
GPIO_B[5]
GPIO_B[4]
GPIO_B[3]
GPIO_B[2]
GPIO_B[1]
GPIO_B[0]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
UT_RX
UT_TX
ND_nWE
nCS[3]
nCS[2]
nCS[1]
nCS[0]
SD_nCS
SD_CKE
FGPIO[10] / SCL
FGPIO[9] / SDA
FGPIO[8]
ADIN_0
ADIN_2
ADIN_4
XIN
XOUT
XFILT
XTIN
XTOUT
TDI
TMS
TCK
TDO
nTRST
MODE1
PKG1
nRESET
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO_USB
VDD_OSC
Ball Type Description – TCC768
L7 I/O GPIO_B[26] / USB_DP
K10
I/O
GPIO_B[25] / I2S Interface Data In. Should be connected externally to
ADCDAT pin.
GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out.
K11 I/O The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
K12 I/O GPIO_B[23] / I2S Interface Master Clock.
GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK.
L11
I/O
The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
Internal pull-down resistor is active at power up.
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
J9
I/O
The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
Internal pull-down resistor is active at power up.
L9
I/O GPIO_B[9 ] / UART RX Signal
M10 I/O GPIO_B[8] / UART TX Signal
L10 I/O GPIO_B[7] / Write Enable for NAND Flash
H6 I/O GPIO_B[5] / External Chip Select 3
J6 I/O GPIO_B[4] / External Chip Select 2
K6 I/O GPIO_B[3] / External Chip Select 1
J5 I/O GPIO_B[2] / External Chip Select 0
L6 I/O GPIO_B[1] / Chip select for SDRAM
J8 I/O GPIO_B[0] / SDRAM clock control
G2 I/O GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
A9 I/O GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
G1 I/O GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
G10 AI General purpose multi-channel ADC input 0
F10 AI General purpose multi-channel ADC input 2
E10 AI General purpose multi-channel ADC input 4
Clock Pins
Main Crystal Oscillator Input for PLL. 12MHz Crystal must
H8
I be used if USB Boot Mode is required. Input voltage must
not exceed VDD_OSC (1.95V max).
G9
O Main Crystal Oscillator Output for PLL
G12 AO PLL filter output. 350pF(±10%) capacitor is required.
K9
I
Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
J10 O Sub Crystal Oscillator Output
JTAG Interface Pins
C11
I JTAG serial data input. External pull-up resistor is required.
D11
I JTAG test mode select. External pull-up resistor is required.
C10
I JTAG test clock. External pull-up resistor is required.
D10 I/O JTAG serial data output. External pull-up resistor is required.
B10
I JTAG reset signal. Active low.
Mode Control Pins
B11
I Mode Setting Input 1. Pull-down for normal operation.
J7
I Package ID1. Pull-up for normal operation.
J12
I System Reset. Active low.
Power Pins
F5 PWR Digital Power for I/O (3.3V)
L1 PWR Digital Power for I/O (3.3V)
H9 PWR Digital Power for I/O (3.3V)
D7 PWR Digital Power for I/O (3.3V)
A8 PWR Digital Power for I/O (3.3V)
D2 PWR Digital Power for I/O (3.3V)
A6 PWR Digital Power for I/O (3.3V)
M12 PWR Power for USB I/O (3.3V)
M11 PWR Digital Power for Oscillators (1.8V)
Preliminary
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