TCC76 Datasheet, PDF (205/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
Sub-registers of NAND type memory
In case of NAND flash type memories, there are several sub-registers for generating command,
address, and data cycles.
Followings are these sub-registers. (M is base field of CSCFGx register)
Except the data register (NDDATA), the sub-register has implicit size of 32bit, so the bus-width
of CSCFGx register does not affect the cycle of command and address registers. It only affects
the cycle of data register.
Command Cycle Register (NDCMD)
0x10000000 * M
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDCMD3
NDCMD2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDCMD1
NDCMD0
*) If bus width of NAND flash is more than 8bit, the NDCMD1 ~ 3 may be used as command register,
otherwise only NDCMD0 is used as command register. The following values are an example commands for
NAND flash of SAMSUNG. Refer to corresponding datasheet of NAND flash chip for more detailed list of
command s.
0x00/0x01 : Page Read Command
0x80 : Page Program Command
0x60 : Block Erase Command
0x70 : Status Read Command
(generated by reading from 0xM0000700 address)
Linear Address Cycle Register (NDLADR)
0x10000000 * M + 0x04
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDLADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDLADR[15:0]
*) By writing to this register, memory controller generates linear address cycle for NAND flash.
Row Address Cycle Register (NDRADR)
0x10000000 * M + 0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDRADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDRADR[15:0]
*) By writing to this register, memory controller generates row address cycle for NAND flash.
Table 15.3 represents the relation between each cycle and address generation.
User must set this information appropriately to PSIZE and CADR field of CSCFGx register
ahead of accessing NAND data.
Preliminary
15-13