TCC76 Datasheet, PDF (225/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
FAST GPIO
19 FAST GPIO
19.1 Description
In the TCC76x, there is special I/O facilities that enable high speed access for I/O port.
These ports are shared with normal GPIO pins and can be accessed through some special
instructions of dedicated coprocessor for these I/O. The dedicated coprocessor number is
5, so user can access these ports by using coprocessor instruction of ARM.
Because there is no control signal to select between the two method (fast GPIO mode and
normal GPIO mode), it is mandatory to clear one set of registers for these two method.
For example, to use Fast GPIO, user must clear corresponding normal GPIO data and
direction control register to zero, and vice versa.
Besides of fast I/O port accessing, the dedicated coprocessor has additional functions for
various purposes. It has bit-reversing functions on the 32bit or 12bit data. And it can
calculate the number of leading zero of 32bit data.
The following table shows coprocessor register for the above functions.
Name
C0
C1
Opcode1
0
1
0
1
2
3
Table 19.1 Register of Fast GPIO
Description
It is for I/O direction and I/O data control.
Bit allocation of C0 register is as follows.
C0[14:0] : FGPDATA(Fast GPIO Data Register) [14:0]
FGPDATA[7:0] are shared with GPIO_A[7:0]
FGPDATA[14:8] are shared with GPIO_A[14:8] / GPIO_D[21:15]
C0[15] : Not used
C0[30:16] : FGPCON(Fast GPIO Control Register) [14:0]
C0[31] : Selection control for FGPDATA[14:8] path.
0 : FGPDATA[14:8] are shared with GPIO_D[21:15]
1 : FGPDATA[14:8] are shared with GPIO_A[14:8]
It is for toggling C0 register bit-by-bit method.
It is for accessing C1 register.
It is for getting 32bit reverse information of C1 register.
It is for getting 12bit reverse information of C1 register.
It is for getting the number of leading zero of C1 register.
To access the above registers, user must use the following instructions.
Instruction
MCR p5, 0, Rd, Cn, Cn, 0
MRC p5, 0, Rd, Cn, Cn, 0
MCR p5, 1, Rd, C0, C0, 0
MRC p5, 1, Rd, C1, C0, 0
MRC p5, 2, Rd, C1, C0, 0
MRC p5, 3, Rd, C1, C0, 0
Table 19.2 Instruction of CP5
Description
To write Cn register as Rd value.
To read Cn register on Rd register.
To invert Fast GPIO, set certain bit field on Rd using this code.
To get the 32bit-reverse of C1 register on Rd register.
To get the 12bit-reverse of C1 register on Rd register.
To get the number of leading zero in C1 register on Rd register.
Note: Fast GPIO register access is guaranteed up to 90MHz of FCLK frequency. Do
not access Fast GPIO reigisters when FCLK frequency exceeds the limit.
Preliminary
19-1