TCC76 Datasheet, PDF (193/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
15 MEMORY CONTROLLER
15.1 Overview
The TCC76x has a memory controller for various kind of memory for digital media en-decoding
system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories,
and also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width
through the GPIO pin or each configuration register. The data bus width can be configured for
each chip select separately
The memory controller provide the power saving function for SDRAM (self refresh).
The following figure represents the block diagram of memory control unit.
SDCFG
Remap
Flag
CSCFGn
SDRAM
State
Machine
Refresh
Controller
SDRAM
Signal
Generator
Signal Mixer
ExtMEM
Signal
Generator
ExtMEM
State
Machine
Memory
Control
Signals
Figure 15.1 Memory Controller Block Diagram
The registers for memory controller block have the base address of 0xF0000000.
Preliminary
15-1