TCC76 Datasheet, PDF (135/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
USB CONTROLLER
USB DMA Control Register (DMACON)
0x800005C0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EOT
Reserved
RUN CKSEL
Bit Name Type Reset
Description
6:5 EOT R/W 00 Force EOT. For test purpose only. Do not write in normal operation.
2:1 RUN R/W
00 Start DMA Command for EP1 and EP0 respectively. DREQ/DACK
signaling between the USB core and the central AHB DMA controller is
enabled only when one/all of these bits are set. Once set, these bits are kept
asserted until cleared by corresponding EOT(End of Transfer) signal from the
central AHB DMA controller. Writing a “0” has no effect on these bits.
These bits are forced to “0” when the corresponding “DMA” bit of IN CSR2
Register is disabled.
0 CKSEL R/W
0 Clock Select for System Bus interface. By default (0), divided HCLK clock is
used for the system bus interface logic of USB core. When this bit is set as
“1”, the clock divider is bypassed and HCLK is directly used. Do not enable
this bit if HCLK frequency is above 60MHz.
USB DMA EP1 FIFO Register (DMAEP1)
15 14 13 12 11 10 9 8 7
Reserved
0x800005C4
6543210
EP1 FIFO Data Port for DMA Controller
USB DMA EP2 FIFO Register (DMAEP2)
15 14 13 12 11 10 9 8 7
Reserved
*) Do not access FIFO registers during DMA operation.
0x800005C8
6543210
EP2 FIFO Data Port for DMA Controller
9.3 USB Device DMA Operation
DMA operations can be started by setting the “DMA” bit (Bit[4]) of IN CSR2 Register and “RUN” bits (Bit[2:1])
of “USB DMA Control Register” described above. Before enable these bits, the USB core and the central AHB
DMA controller must be programmed correctly. Be careful about the endpoint directions programmed in the
USB core and Source/Destination addresses programmed in central AHB DMA controller.
Source or Destination address must be one of DMAEP1(0x800005C4) and DMAEP2(0x800005C8). Do not
use EP1FIFO and EP2FIFO register address.
9.3.1 OUT Endpoint DMA Operation
After the USB core receives OUT data (≤ maximum packet size) from HOST, the endpoint which took the data
will generate DREQ strobe to AHB DMA Controller as far as the FIFO isn't empty. Consequently, the number
of DREQs will be equal to the number of data bytes from Host. The DMA controller can read data from the
FIFO in the specific endpoint by issuing the DACK input to the core. Whenever one packet is transferred
successfully from HOST to USB, the process described above shall be performed for the OUT endpoint DMA
operation. This operation is repeated until EOT signal is asserted from the DMA Controller.
9.3.2 IN Endpoint DMA Operation
As long as the FIFO isn't full, DREQ signal is asserted to the DMA Controller. Then, DMA controller may write
one packet of data (≤ maximum packet size) or multiple packets of data to a specific IN endpoint FIFO with
DACK until EOT is asserted.
Preliminary
9-13