TCC76 Datasheet, PDF (107/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
8 CLOCK GENERATOR
8.1 Overview
The TCC76x has a lot of peripherals with different operating frequency. To provide an appropriate clock to
each peripheral, the TCC76x has a clock generator unit. There is also a power management feature that can
manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode.
PWRDN
XIN
PLLmode
WAITGEN
[18]
i_XIN
WAIT
PLL
PLLOUT
XTIN
MUX
MUX
PWDCTL[17]
PLLDIVCLK
Divider
MUX
DIVCLK0
FCLK GEN
PWDCTL[16] SCLKmode[5:0]
MUX
DIVCLK1
SCLKmode[13:8]
HCLK GEN
PWDCTL[9:8]
FCLK (CPU)
HCLK (AHB)
MUX
[15:14]
DCLKmode
DCLK GEN
DCLK (GSIO)
MUX
[15:14]
EX1CLKmode
EX1CLK
GEN
EX1CLK (External)
MUX
[15:14]
EX2CLKmode
EX2CLK
GEN
EX2CLK (I2C)
MUX
[15:14]
UTCLKmode
UTCLK
GEN
UTCLK (UART)
MUX
[9:8]
UBCLKmode
USBCLK
GEN
UHCLK (USB Host)
UDCLK (USB Device)
MUX
[9:8]
PXCLKmode
LCLK GEN
LCLK (LCD)
MUX
[9:8]
TCLKmode
TCLK GEN
TCLK (Timer/Counter)
MUX
[9:8]
GCLKmode
GCLK GEN
GCLK (DAI)
MUX
[7:6]
ADCLKmode
ADCLK
GEN
ADCLK (ADC)
MUX
[7:6]
CIFCLKmode
CIFCLK
GEN
CIFCLK (Camera I/F)
Figure 8.1 Clock Generator Block Diagram
WAITGEN module is for waiting until oscillation is stabilized. It blocks internal clocks until about 2¹⁸
transitions occur on XIN after reset is released. If frequency of XIN is 16MHz, the wait time is about 16.4 ms
(21.85ms @12MHz). The source of the system clocks (FCLK and HCLK) can be selected among XIN (main
oscillator), PLLOUT (PLL output clock) and XTIN (sub-oscillator). The other clocks that are dedicated to each
Preliminary
8-1