TCC76 Datasheet, PDF (72/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CPU
3.3 Clock Modes
3.3.1 About clocking modes
The ARM940T has two clock inputs HCLK and FCLK that allow flexible clocking
configurations. There are three different modes of operation, selected using bits 30
and 31 of CP15 register 1 (C1), the control register. These modes are:
FastBus
Synchronous
Asynchronous
The TCC76x does not support Synchronous Mode. Do not enable Synchronous
Mode.
The ARM940T is a pseudo-static desing and both clocks can be stopped. Typically
when accessing slow memory systems or peripherals, wait states are applied using
the HREADY signal. Refer to AMBA Specification for more details.
3.3.2 FastBus mode
In this mode of operation the HCLK input is used to control:
the internal ARM9TDMI
cache operations
the AMBA bus interface
The FCLK input is ignored. This mode is typically used in systems with high-speed
memories.
3.3.3 Asynchronous mode
This mode is typically used in systems with low-speed memory. In this mode both
the HCLK and FCLK inputs are used. HCLK is used to control the AMBA bus
interface. FCLK is used to control the internal ARM9TDMI processor core and any
cache operations. The one restriction is that FCLK must have a higher frequency
than HCLK. An example is shown in Figure 3.3.
HCLK
FCLK
Figure 3.3 Asynchronous Clocking Mode
If the ARM940T performs an external access, the ARM940T switches to HCLK to
perform the access. The delay when switching from FCLK to HCLK is a minimum
of one HCLK cycle and a maximum of one and a half of HCLK cycles. An example
of the clock switching is shown in Figure 3.4. When switching from HCLK to
FCLK, the maximum delay is one FCLK cycle and the maximum delay is one and a
half of FCLK cycles.
HCLK
FCLK
ECLK
Figure 3.4 Switching from FCLK to HCLK in asynchronous mode
Preliminary
3-6