TCC76 Datasheet, PDF (189/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
LCD Status Register (LSTATUS)
0x80000F44
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
EF DD RU FU
FIELD
Description
Even-Field(Read-Only)
EF [3]
0: odd field or frame
1: even field or frame
Disable Done(Read/Clear).
DD* [2]
If LEN is disabled, DD will be 1 after current frame has been
displayed.. As MDD of LIM register is cleared, it can be LCD interrupt
source
Register Update(Read/Clear)
RU*[1]
It indicates that all registers programmed are applied to current frame
data. As MRU of LIM register is cleared, it can be LCD interrupt
source.
FIFO underrun(Read/Clear)
FU*[0]
It indicates that FIFO underrun has been occurred. In this case, LCLK
frequency must be lower. As MFU of LIM register is cleared, it can be
LCD interrupt source.
For clearing a specified bit, it must be written to 1. If a interrupt is generated, LSTATUS
bits, which correspond to the interrupt sources, must be cleared. Otherwise, the uncleared
interrupt will be not generated any more.
LCD Interrupt Masking Registers (LIM)
0x80000F48
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
MDD MRU MFU
FIELD
MDD[2]
MRU[1]
MFU[0]
Description
Mask “Disable Done Interrupt”.
Mask “Register Update Interrupt”.
Mask “FIFO underrun(Read/Clear)”.
LCD Image Position(LIP)
0x80000F4C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Y[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X[10:0]
FIELD
Y [10:0]
X [10:0]
Y position to display
X position to display
Description
Preliminary
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