TCC76 Datasheet, PDF (232/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
BOOTING PROCEDURE
20.5 External ROM Boot with Encryption (BM == 100)
The NOR flash must be connected via nCS3 signal. The boot sequence of this mode
is as follows.
i) Read init line from NOR flash. The init line consists of the following information.
1^st word ~ 2^nd word: security information
3^rd word : size of initialization code.
ii) If 1^st or 2^nd word is 0xFFFFFFFF, it goes to USB boot mode for F/W downloading.
iii) If 1^st and 2^nd word don’t contain security information, then it calculates CRC-32 for
the 1^st 512kbytes of NOR flash and compare the CRC-32 code with 6^th word of NOR
flash. If the CRC checking is success, it goes to external NOR boot by jumping
0x70000000. Or if the CRC check is failed, it goes to USB boot mode for F/W
downloading.
iv) If the 1^st and 2^nd word are correct, read initialization code from the next data of init
line, and copy them to internal SRAM (starts from 0x30000000). After all amount of
codes are copied (initialization codes are not encrypted), the program make a call
(branch with link) command to internal SRAM (0x30000000). The initialization code
must be encapsulated by the entrance command of ‘STR LR, [SP - #4]!’, and the exit
command of ‘LDR PC, [SP], #4’.
v) The initialization code must make arrange the memory area so that the zero base area
(0x00000000 ~ 0x0FFFFFFF) can contain the main F/W code and then goes back to
booting sequence while setting r0 register to the start address of F/W code.
vi) Read the size of F/W code at the address designated by r0 register.
vii) The F/W code is read from the next address of the r0 register and decrypted and
copied to the zero base area (0x00000000 ~ 0x0FFFFFFF).
viii) After all of amount of F/W codes are decrypted and copied, the program jumps to
0x00000000.
Figure 20.4 illustrates the allocation map of encrypted F/W code in NOR flash.
0x70000000
0x70000010
4 byte
S₀
Init Line of NOR flash
S₁
S_A
Initialization Code Area (S_A bytes)
.
.
.
Returning from these area, the register R0 contains
the start address of F/W code
Size of F/W
R0
S_B
Main F/W Code Area (S_B bytes)
Figure 20.4 Allocation of encrypted F/W code
Preliminary
20-6