TCC76 Datasheet, PDF (108/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
peripheral can be driven by one of three clock sources (XIN, PLLOUT, XTIN) or divided PLL output.
Each clock generation module has two modes of clock division - normal divider mode and DCO mode that is
described below. The two modes can be selected by DIVMODE register.
8.1.1 DCO Control
DCLK is used as the master clock of DAI (Digital Audio Interface) block if it is in
master mode. EXTCLK is used for external usage especially for CD application.
UTCLK is used as the main clock of UART controller.
These clocks are generated by 14bit DCO (Digital Controlled Oscillator) that can
generate a stable and flexible frequency as long as its frequency is below about one
tenth of the divisor clock. That is, if the frequency of DCO source clock is more than
ten times of that of DCO output clock, the jitter of DCO output clock can be less than
10%.
For reliable operation of DAI, the frequency of divisor clock must be higher than
about 240MHz as the frequency of DCLK usually has about 10 to 22 MHz. The
target frequency can be acquired by writing the phase value calculated by the
following equation to each PHASE register.
D_PHASE
EX1_PHASE
EX2_PHASE
UT_PHASE
= 16384 * f_DCLK / f_DIV
= 16384 * f_EX1CLK / f_DIV
= 16384 * f_EX2CLK / f_DIV
= 16384 * f_UTCLK / f_DIV
Where, f_DIV is the frequency of divisor clock that is normally frequency of PLLOUT
clock. For example, when you use 44.1KHz sampling rate and want to set DCLK as
256fs, the target frequency of DCLK is 256 * 44.1k = 11.2896 MHz, and if you set
PLL to 266MHz, the D_PHASE value must be set to 696 (~= 16384 * 11.2896 / 266).
The other clocks have 6bit DCO, so the formula for setting frequency is different
from that of 14bit DCO clocks. The main difference is that the multiplication factor is
changed to 64 instead of 16384. For 6bit DCO clocks, they have poorer resolution
than that of 14bit DCO clocks. So it is strongly recommended to use n power of 2 as
a phase value of those clocks. In that case, the DCO simply act as a clock divider
circuit. For example, if the source clock of DCO has 200MHz, the preferred
frequencies for it are 100MHz, 50MHz, 25MHz, 12.5MHz, etc.
For both type of DCOs, it has limited frequency that can be generated with it. The
maximum frequency of DCO is a half of its divisor clock’s frequency. But, by setting
to 0 at its phase value, it is possible to get the same frequency as its divisor clock’s
frequency.
Table 8.1 Example of Phase for Several Target Frequencies
Target
6bit DCO 14bit DCO
Description
f_IN
f_IN / 2
f_IN / 4
f_IN / 8
f_IN / 16
f_IN / 32
0x00
0x20
0x10
0x08
0x04
0x02
0x0000
0x2000
0x1000
0x0800
0x0400
0x0200
Bypass (f_OUT = f_IN)
Divide by 2 (f_OUT = f_IN / 2)
Divide by 4 (f_OUT = f_IN / 4)
Divide by 8 (f_OUT = f_IN / 8)
Divide by 16 (f_OUT = f_IN / 16)
Divide by 32 (f_OUT = f_IN / 32)
Preliminary
8-2