TCC76 Datasheet, PDF (100/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
GPIO PORT
7.2 Register Description
Table 7.1 GPIO Register Map (Base Address = 0x80000300)
Name
Addr
Type
Reset
Description
GDATA_A
0x00
R/W
0xFFFFFFFF GPIO_A Data Register
GIOCON_A
0x04
R/W
0x00000000 GPIO_A Direction Control Register
GSEL_A
0x08
R/W
0x00000000 GPIO_A Function Select Register 1
GTSEL_A
0x0C
R/W
0x00000000 GPIO_A Function Select Register 2
GDATA_B
0x10
R/W
0x3FFFFFFF GPIO_B Data Register
GIOCON_B
0x14
R/W
0x000000FF GPIO_B Direction Control Register
GSEL_B
0x18
R/W
0x3C0000FF GPIO_B Function Select Register 1
GTSEL_B
0x1C
R/W
0x00000000 GPIO_B Function Select Register 2
GDATA_C
0x20
R/W
0xFFFF
GPIO_C Data Register
GIOCON_C
0x24
R/W
0x0000
GPIO_C Direction Control Register
GDATA_D
0x30
R/W
0x007FFF GPIO_D Data Register
GIOCON_D
0x34
R/W
0x000000 GPIO_D Direction Control Register
Reset values are valid only for the TCC761. All the other derivatives of the TCC76x may have different reset
values. For those bits without external pins, reset values should not be changed. Read-modify-write sequence
is recommended for all the GPIO registers
Special GPIO pins
A special GPIO register (MCFG register) exists in Memory controller. It can control
MODE0(READY) pin and SD_CLK pin as general purpose input and output pin each
other.
That is, by setting appropriate field of MCFG register, user can monitor the state of
MODE0(READY) pin and can manipulate the state of SD_CLK pin as low or high.
Refer to Chapter 15 for more information of MCFG register.
GPIO_A Data Register (GDATA_A)
0x80000300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data for GPIO_A[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_A[15:0] pin
If a certain GPIO_A pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_A pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_A pin; Low or High.
GPIO_A Direction Control Register (GIOCON_A)
0x80000304
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Direction control for GPIO_A[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_A[15:0] pin
If a bit is set to 1, the corresponding GPIO_A pin is set to output mode. If set to 0, the
corresponding GPIO_A pin is set to input mode.
Preliminary
7-2