TCC76 Datasheet, PDF (117/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
UBCLK (USB) Control Register (UBCLKmode)
0x8000041C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DIVUB
0
UB_PHASE[5:0]
UBCLK is used as the main clock of both USB Host and Device block.
Bit Name
Type Default Description
31:10 Reserved
R
0 Reserved
9:8 DIVUB
R/W 0 UBCLK Divisor Clock Select
DIVUB f_DIVUB (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
7:6 Reserved
R
0 Reserved
5:0 UB_PHASE R/W 0 UBCLK Clock Frequency Select
DIVMODE[8] UB_PHASE f_UBCLK (UBCLK Frequency)
0
0
f_DIVUB
0
1 ~ 0x20 f_DIVUB * UB_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIVUB / (UB_PHASE + 1)
UBCLK is gated separately by “UBH” bit and “USB” bit of CKCTRL register to generate UHCLK (for Host
Controller) and UDCLK (for Device Controller).
LCLK (LCD) Control Register (LCLKmode)
0x80000420
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DIVLCD
0
LCD_PHASE[5:0]
Bit Name
Type Default Description
31:10 Reserved
R
0 Reserved
9:8 DIVLCD
R/W 0 LCLK Divisor Clock Select
DIVLCD f_DIVLCD (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
7:6 Reserved
R
0 Reserved
5:0 LCD_PHASE R/W 0 LCLK Clock Frequency Select
DIVMODE[9] LCD_PHASE f_LCLK (LCLK Frequency)
0
0
f_DIVLCD
0
1 ~ 0x20 f_DIVLCD * LCD_PHASE / 2⁶
0
> 0x20 Undefined. Do not use.
1
X
f_DIVLCD / (LCD_PHASE + 1)
LCLK is also controlled by LCK bit of CKCTRL register that can enable or disable LCLK. If this bit is set to high,
LCLK is disabled and if it is low, LCLK is enabled.
To avoid LCD FIFO underrun, LCLK frequency must be set below HCLK frequency.
f_LCD < f_HCLK
Preliminary
8-11