TCC76 Datasheet, PDF (186/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
LCD Vertical Timing Register1 (LVTIME1)
31 30 29 28 27 26 25 24 23
0
15 14 13 12 11 10 9 8 7
0
22 21 20
654
FLC
0x80000F10
19 18 17 16
FPW
3210
FIELD
FPW [21:16]
FLC [10:0]
Description
TFT/TV : Frame Pulse Width is the pulse width of frame clock
(VSYNC).
STN: N/A
Frame Line Count is the number of lines in each frame on the screen.
LCD Vertical Timing Register2 (LVTIME2)
0x80000F14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
FSWC[8:1]
VD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
FEWC
FIELD
FSWC [8:1]
VD
FEWC [7:0]
Description
TFT/TV: Frame Start Wait Cycle is the number of lines to insert at the
end of each frame. VD is FSWC[0].
STN: FSWC[8:1] is N/A. If VD is set, VSYNC signal starts on
negative falling edge of HSYNC.
TFT/TV: Frame End Wait Cycle is the number of lines to insert at the
beginning of each frame.
STN: extra dummy lines between the end and beginning of frame
LCD Vertical Timing Register3 (LVTIME3)
0x80000F18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
FPW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
FLC
If NI of LCTRL is 0, LVTIME3 and LVTIME4 is for even-field. Otherwise, LVTIME3
and LVTIME4 must be the same with LVTIME1 and LVTIME2.
LCD Vertical Timing Register4 (LVTIME4)
0x80000F1C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
FSWC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
FEWC
Preliminary
14-18