TCC76 Datasheet, PDF (18/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
Pin # Type Description – TCC760
XD[3:0]
NCS[3:0]
ND_nWE
nWE
nOE
READY
ND_nOE[3:0] / GPIO_B[5:2]
GPIO_B[7]
128:125
50:47
57
58
59
73
External Bus Chip Select [3:0] / NAND Flash Output Enable
I/O
[3:0] / GPIO_B[5:2]
I/O NAND flash WE. Active low. / GPIO_B[7]
I/O Static Memory Write Enable signal. Active low.
I/O Static Memory Output Enable signal. Active low.
I Ready information from external device.
USB/UART/IrDA Interface Pins
USB_DP
USB_DN
USBH_DP
USBH_DN
UT_TX
UT_RX
GPIO_B[26]
GPIO_B[27]
GPIO_B[28]
GPIO_B[29]
GPIO_B[8] / SD_nCS
GPIO_B[9] / IDE_nCS1
51
I/O USB Function D+ signal / GPIO_B[26]
52
I/O USB Function D- signal / GPIO_B[27]
53
I/O USB Host D+ signal / GPIO_B[28]
54
I/O USB Host D- signal / GPIO_B[29]
UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip
60
I/O
Select
61
I/O UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
Audio Interface Pins
BCLK
LRCK
MCLK
DAO
DAI
GPIO_B[21] / BM[0]
GPIO_B[22] / BM[1]
GPIO_B[23]
GPIO_B[24] / BM[2]
GPIO_B[25]
62
I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0
63
I/O I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1
66
I/O I2S System Clock / GPIO_B[23]
I2S Digital Audio data Output / GPIO_B[24] / Boot Mode
67
I/O
Bit 2
68
I/O I2S Digital Audio data Input / GPIO_B[25]
CD DSP Interface Pins
CBCLK
CLRCK
CDAI
GPIO_A[1]
GPIO_A[2]
GPIO_A[3]
105
I/O CD Data Bit Clock Input / GPIO_A[1]
106
I/O CD Data Word Clock Input / GPIO_A[2]
107
I/O CD Data Input / GPIO_A[3]
External Interrupt Pins
EXINT[3]
EXINT[2:0]
GPIO_A[15]
124
GPIO_A[14:12] / FGPIO[14:12] 123:121
I/O External Interrupt Request [3] / GPIO_A[15]
I/O External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12]
Camera Interface Pins
CISHS
CISVS
CISCLK
CISD[7:4]
CISD[3:0]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
GPIO_D[21:18]
GPIO_A[3:0]
92
I/O Horizontal Sync. Input / GPIO_D[17]
91
I/O Vertical Sync. Input / GPIO_D[16]
90
I/O Clock Input / GPIO_D[15]
96:93
I/O Data Input[7:0] / GPIO_D[21:18], GPIO_A[3:0]
107:104
General Purpose I/O Pins
GPIO_A[15]
GPIO_A[14:12]
EXINT[3]
EXINT[2:0] / FGPIO[14:12]
GPIO_A[11]
GPIO_A[10]
GPIO_A[9] / BW[1]
GPIO_A[8] / BW[0]
SDI2 / FGPIO[11] / SCL
FRM2 / FGPIO[10] / SDA
SCK2 / FGPIO[9] / SCL
SDO2 / FGPIO[8] / SDA
GPIO_A[7:4]
GPIO_A[3:1]
SDI1 / FGPIO[7]
FRM1 / FGPIO[6]
SCK1 / FGPIO[5]
SDO1 / FGPIO[4]
SDI0 / CDAI / FGPIO[3]
FRM0 / CLRCK / FGPIO[2]
SCK0 / CBCLK / FGPIO[1]
124
123:121
118:115
114
113
111
108
107:105
I/O GPIO_A[15] / External Interrupt 3
I/O GPIO_A[15:12] / External Interrupt 3 ~ 0 / Fast GPIO bits 14 ~ 12
GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2
Fast GPIO bits 11 ~ 8 / I2C signals.
I/O The status of BW[1:0] is latched at the rising edge of nRESET and
used to determine external bus width. Refer to section “MEMORY
CONTROLLER” for BW[1:0] description.
I/O GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4
GPIO_A[3:1] / General Purpose Serial I/O 0 / CD Interface Signals /
I/O
Fast GPIO bits 3 ~ 1
Preliminary
1-8