TCC76 Datasheet, PDF (28/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
GPIO_A[0]
GPIO_B[29:28]
GPIO_B[27:26]
SDO0 / FGPIO[0]
USBH_DN, USBH_DP
USB_DN, USB_DP
GPIO_B[25]
GPIO_B[24] / BM[2]
GPIO_B[23]
GPIO_B[22] / BM[1]
GPIO_B[21] / BM[0]
DAI
DAO
MCLK
LRCK
BCLK
GPIO_B[9]
GPIO_B[8]
GPIO_B[7]
GPIO_B[5:2]
GPIO_B[1]
GPIO_B[0]
GPIO_D[19]
GPIO_D[18]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
ADIN_0
ADIN_2
ADIN_4
UT_RX
UT_TX / SD_nCS
ND_nWE
nCS[3:0]
SD_nCS / SD_nCLK
SD_CKE
FGPIO[12]
FGPIO[11]
FGPIO[10] / SCL
FGPIO[9] / SDA
FGPIO[8]
XIN
XOUT
XFILT
XTIN
XTOUT
TDI
TMS
TCK
TDO
nTRST
MODE1
PKG1
Ball
C9
M9,L8
K8,L7
K10
K11
K12
L11
J9
L9
M10
L10
H6, J6
K6, J5
L6
J8
H12
D2
G2
A9
G1
G10
F10
E10
H8
G9
G12
K9
J10
C11
D11
C10
D10
B10
B11
J7
Type Description – TCC763/ TCC764
GPIO_A[0] / General purpose serial I/O 0 Serial Data Output
I/O
FGPIO[0]
I/O GPIO_B[29:28] / USBH_DN, USBH_DP
I/O GPIO_B[27:26] / USB_DN, USB_DP
GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
I/O detailed description on BM[2:0].
GPIO_A[24:21] is internally connected with audio CODEC signals.
Refer to Figure 1.3 for more information.
GPIO_B[22:21] have internal pull-down resistor which is
active at power up.
I/O GPIO_B[9 ] / UART RX Signal
I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
I/O GPIO_B[7] / Write Enable for NAND Flash
I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
I/O
SDRAM.
I/O GPIO_B[0] / SDRAM clock control
GPIO_D[19] / Fast GPIO bit 12. Internal pull-up resistor is enabled
I/O
at reset.
GPIO_D[18] / Fast GPIO bit 11. Internal pull-up resistor is enabled at
I/O
reset.
I/O GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
I/O GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
I/O GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
AI General purpose multi-channel ADC input 0
AI General purpose multi-channel ADC input 2
AI General purpose multi-channel ADC input 4
Clock Pins
Main Crystal Oscillator Input for PLL. 12MHz Crystal
I must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
O Main Crystal Oscillator Output for PLL
AO PLL filter output
Sub Crystal Oscillator Input. 32.768kHz is recommended.
I
Input voltage must not exceed VDD_OSC (1.95V max).
O Sub Crystal Oscillator Output
JTAG Interface Pins
I JTAG serial data input for ARM940T
I JTAG test mode select for ARM940T
I JTAG test clock for ARM940T
I/O JTAG serial data output for ARM940T. External pull-up resistor
is required to prevent floating during normal operation.
I JTAG reset signal for ARM940T. Active low.
Mode Control Pins
I Mode Setting Input 1. Pull-down for normal operation.
I Package ID1. Pull-up for normal operation.
Preliminary
1-18