TCC76 Datasheet, PDF (114/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
DCLK (DAI) Control Register (DCLKmode)
0x8000040C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVD
D_PHASE[13:0]
Bit Name
31:16 Reserved
15:14 DIVD
13:0 D_PHASE
Type
R
R/W
R/W
Default Description
0 Reserved
0 DCLK Divisor Clock Select
DIVD f_DIVD (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
0x0800 DCLK Clock Frequency Select
DCLK is also controlled by DAI bit of CKCTRL register that can enable or disable DCLK. If this bit is set to
high, DCLK is disabled and if it is low, DCLK is enabled.
DCLK is for DAI which requires 512*fs frequency. To make DCLK of this frequency, first set the frequency of
PLL (f_DIV) more higher than 512*fs and set D_PHASE according to the above formulae. It is recommended to
set the frequency of PLL by the n power of 2, than the duty ratio of DCLK is only dependant of that of PLL
clock.
Preliminary
8-8