TCC76 Datasheet, PDF (133/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
USB CONTROLLER
OUT CSR1 Register (OCSR1n)
15 14 13 12 11 10 9 8 7 6 5 4
Reserved
CTGL STST ISST FLFF
This register maintains the status information of endpoints.
3
DERR
0x80000550
210
OVER FFL ORDY
CTGL [7] Type
Data Toggle Bit
1
W The data toggle sequence bit is reset to DATA0.
STST [6]
1
0
Type
R
W
STALL Handshake Issued
Indicates that the OUT token is ended with a STALL
handshake. USB issues a stall handshake to the host if
host sends more than MAXP data for the OUT token.
Clear STST flag by writing 0.
ISST [5]
1
0
Type
Issue STALL Handshake
R/W ^{Issue a STALL Handshake to the USB.}
End the STALL condition.
FLFF [4]
1
0
Type
R/W
Issue FIFO Flush
OUT FIFO is flushed.
This bit can be set only when the ORDY flag is set.
Stop flushing FIFO.
DERR [3]
1
Type
R
Data Error
Valid only in ISO mode. This bit should be sampled with
ORDY (Bit[0]). “1” indicates the data packet due to be
unloaded by the CPU has an error (either bit stuffing or
CRC). If two packets are loaded into the FIFO, and the
second packet has an error, then this bit gets set only after
the first packet is unloaded. This bit is automatically
cleared when ORDY gets cleared.
OVER [2]
1
Type
R
OUT FIFO Over Run
Valid only in ISO mode. This bit is set if the core is not
able to load an OUT ISO token into the FIFO. Cleared
by writing 0.
FFL [1]
1
Type
OUT FIFO Full
R Indicates that no more packets can be accepted
ORDY [0] Type
OUT Packet Ready
1
R Indicates the USB has loaded a packet of data into the FIFO.
Clears ORDY flag by writing 0.
0
W Once the CPU reads the FIFO for the entire packet, this bit
should be cleared. (refer ACLR bit of OCSR2n register)
*) FFL == 0 && ORDY == 0 : Indicates that there is no packet in the FIFO.
FFL == 0 && ORDY == 1 : Indicates that there is 1 packet in the FIFO.
FFL == 1 && ORDY == 1 : Indicates that there are 2 packets in the FIFO.
Preliminary
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