TCC76 Datasheet, PDF (112/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
PLL Control Register (PLLmode)
0x80000404
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
LOCK XTE DIV1
S
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
M
00
P
Bit Name
31:21 Reserved
20 LOCK
19 XTE
18 DIV1
17:16 S
15:14 Reserved
13:8 M
7:6 Reserved
5:0 P
Type
R
R
R/W
R/W
R/W
R
R/W
R
R/W
Default Description
0 Reserved
0 PLL Lock Counter Flag indicates that the internal PLL is in lock state.
This flag is generated from a counter, which runs with XIN oscillator
clock input. In case of 12MHz frequency, this bit will be set at about
341µs after PLL is enabled. This bit is cleared when PLL bit (Bit
[11]) of CKCTRL register is set. Do not look up this flag when PLL
S/M/P parameter values are changed.
0 XTIN Enable in Power Down Mode.
0 XTIN is disabled in power down mode
1 XTIN is controlled by XTIN bit of CKCTRL register
This bit has no effect if XTTC32 bit of PWDCTL register is 0 (XTIN is
always enabled).
0 Divisor Clock Select
0 Use Oscillator input as DIVCLK1 and DIVCLK0
1 Use PLL output as DIVCLK1 and DIVCLK0
0 PLL Post-Scaler (0 ≤ S ≤ 3)
0 Reserved
0x2E PLL Main-Divider (1 ≤ P ≤ 62)
0 Reserved
0x0E PLL Pre-Divider (1 ≤ P ≤ 62)
S/M/P
PLL Frequency Setting
S [1:0] Post-Scaler
(0 ≤ S ≤ 3)
M[5:0] Main-Divider
(1 ≤ P ≤ 62)
P [5:0] Pre-Divider
(1 ≤ P ≤ 62)
The PLL output frequency can be acquired by the following equation.
f_PLL = f_Xin * 8 * (M + 2) / ((P + 2) * 2^S )
Where, M, P, S can be set by PLLmode register. Note that not all the M and P
parameter combinations are valid. Make sure to check the stability of the resulting
frequency.
The PLL has a standby mode to minimize power consumption. It is controlled by PLL
bit of CKCTRL register.
Preliminary
8-6