TCC76 Datasheet, PDF (67/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CPU
3 CPU
3.1 Overview
The TCC76x has adopted the ARM940T core for controlling system and processing
various kinds of digital signals. It has a Harvard cache architecture with separate 4Kbyte
data and 4Kbytes instruction caches, each with 4-word of line length.
A protection unit allows eight regions of memory to be defined, each with individual
cache and write buffer configurations and access permissions. The cache system is
software configurable to provide highest average of performance or to meet the needs of
real-time systems.
The followings are key features of ARM940T core.
CPU
Cache
Operating State
Operating Mode
Memory Format
Address Space
Instruction
ARM940T
4KB for Data / 4KB for Instruction
ARM state / THUMB state
7 different modes (SVC/UND/ABT/FIQ/IRQ/SYS/USR)
Little endian (ARM940T itself supports big-endian type also,
but the memory controller in the TCC76x only support for
little-endian type)
32bit of 4Gbyte
32bit (in ARM state) / 16bit (in THUMB state)
Preliminary
3-1