TCC76 Datasheet, PDF (109/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
8.1.2 Power Down Mode
In power down mode, all the clocks including the main oscillator (XIN) can be disabled for maxmum power
saving. There are three possible cases in power down mode.
1. All the clocks stopped
2. 32-bit counter running with XTIN clock input.
3. All or part of the peripherals running with XTIN clock input.
The XTIN clock can be managed to remain enabled, by setting either XTE bit of PLLmode to 1 or XTTC32 bit
of PWDCTL to 0. (Refer to Figure 8.2 for control bit usages).
Before power down mode is enabled, “Interrupt Enable Register” and “Wakeup Event Register” must be
programmed appropriately. Any bit enabled in these registers can wakeup the system from the power down mode.
If sub-oscillator (XTIN) is not used or disabled in power down mode (case 1 above), only the external interrupt
pins (GPIO_A[15:12]/EXINT[3:0]) can wake up the system. In this case, the corresponding bit(s) of “Wakeup
Event Register” must be enabled. Refer to Section “Interrupt Controller” for “Wakeup Event Register”
description.
When HCLK is stopped (case 2 above), the TCC76x interrupt controller stops immediately and does not work.
Only the following events are masked by “Wakeup Event Register” and sent to the clock wakup circuitry.
- 32-bit timer interrupt
- external interrupt pins (GPIO_A[15:12]/EXINT[3:0])
It is recommended to disable “Interrupt Enable Register” and use “Wakeup Event Register” in all cases.
Right after exit from power down mode, the XIN crystal starts oscillation and the processor waits until the input
frequency is stabilized, and continues to operate at the next instruction. Note that the XTIN input has no wait
logic for crystal stabilization. Thus, do not disable XTIN oscillator input when the CPU is running with XTIN.
Power down mode can be entered by writing a “1” to PDN bit of CKCTRL register.
8.1.3 IDLE Mode
In idle mode, the FCLK of the ARM940T is disabled and HCLK can be disabled optionally by using HD bit of
SCLKmode register.
Before Idle mode is enabled, “Interrupt Enable Register” and “Wakeup Event Register” must be programmed
appropriately. Any bit enabled in these registers can wakeup the system from the Idle mode.
As explained in previous section, the TCC76x interrupt controller does not work when HCLK is stopped. So,
make sure to disable “Interrupt Enable Register” and use “Wakeup Event Register” if HCLK is to be stopped.
Idle mode can be entered by writing a “1” to IDLE bit of CKCTRL register. Refer to the description of
PWDCTL and HCLKSTOP register for additional power control options which can be used in idle mode.
Preliminary
8-3