TCC76 Datasheet, PDF (167/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
DMA CONTROLLER
REP [1]
0
1
Repeat Mode Control
After all of hop transfer has executed, the DMA channel is
disabled
The DMA channel remains enabled. When another DMA request has
occurred, the DMA channel start transfer data again with the same
manner (type, address, increment, mask) as the latest transfer of that
channel.
EN [0]
0
1
DMA Channel Enable
DMA channel is terminated and disabled.
It does not affect the HCOUNT register, so if the current hop counter is
not zero when channel is disabled, it is possible that the transfer illegally
starts right after channel is re-enabled. Make sure that HCOUNT is
zero not to continue transfer after channel is re-enabled.
DMA channel is enabled. If software type transfer is selected,
this bit generates DMA request directly, or if hardware type
transfer is used, the selected interrupt request flag generate
DMA request.
Channel Configuration Register(CHCONFIG)
0x80000E2C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IS1 IS0
MIS1 MIS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWP1 SWP0
PRI
FIX
IS1 [22]
Channel 1 Alternate interrupt status
0
No interrupt in channel 1
1
Channel1 Interrupt is occurred
Without regard to Interrupt enable bit(IEN) of channel1, this bit indicates the channel1 interrupt
status.
This bit is automatically cleared when FLAG bit of channel1 is cleared. This bit is read only.
IS0 [21]
Channel 0 Alternate interrupt status
0
No interrupt in channel 0
1
Channel1 Interrupt is occurred
Except for channel difference, This bit is the same as IS1 bit.
MIS1[17]
0
1
Channel1 Masked Interrupt Status
Masked interrupt is not occurred in channel 1
Channel1 Masked Interrupt is occurred
This bit is set when channel1 interrupt occurs and interrupt enable bit (IEN) of channel1 is set.
This bit is automatically cleared when FLAG bit of channel1 is cleared. This bit is read only.
MIS0[16]
0
1
Channel0 Masked Interrupt Status
Masked interrupt is not occurred in channel 0
Channel0 Masked Interrupt is occurred
Except for channel difference, This bit is the same as MIS1 bit.
Preliminary
13-7